The present invention relates to an output buffer device including a booster circuit for semiconductor memory devices.
A conventional buffer device of such a kind is shown in FIG. 4. The buffer circuit, which is incorporated in a semiconductor memory device, has a pull-up transistor 1, a pull-down transistor 2, and a booster circuit 3. When a signal S2 of a HIGH level is inputted to an input terminal 6 of the pull-up transistor 1, an output terminal 4 of the buffer device is pulled up or charged up to a potential of a power source. Also, when a signal #S1 of a HIGH level is inputted to an input terminal 7 of the pull-down transistor 2, the output terminal 4 is pulled down to a potential of a ground. In addition, when a signal S1 of a HIGH level is inputted to an input terminal 8 of the booster circuit 3, a boosted HIGH signal S2 is outputted from an output terminal 9 of the booster circuit 3, and when a signal S1 of a LOW level is inputted to the input terminal 8, a LOW signal S2 is outputted from the output terminal 9. The input terminal 8 of the booster circuit 3 and the input terminal 7 of the pull-down transistor 2 are connected by means of an inverter 5. Thus, a data signal S1 applied to the input terminal 8 of the booster circuit 3 and a data signal #S1 applied to the input terminal 7 of the pull-down transistor 2 are mutually inverse.
The buffer device in the semiconductor memory device functions as described below. It is assumed in this description that data stored in data memory area (not shown in the figure) of the semiconductor memory device has a value of 1 at address (1,1), 0 at address (0,1), and 1 at address (0,0). The data stored in addresses (1,1) and (0,0) in this semiconductor memory device will be sequentially read and outputted from the output terminal 4.
First, as shown in FIG. 5 (a), when address signals A0 and A1 are both HIGH, the data "1" is read from address (1,1), and a HIGH-level signal S1 as shown in FIG. 5 (b) and expressing the data value "1" is inputted to the booster circuit 3 and the inverter 5. Thus, a HIGH signal S2 boosted by the booster circuit 3 as shown in FIG. 5 (c) is inputted to the input terminal 6 of the pull-up transistor 1. Also, a LOW signal #S1, resulting from inversion of the signal S1 by the inverter 5, is inputted to the input terminal 7 of the pull-down transistor 2. As a result, an output electric current of the pull-up transistor 1 increases, and the output terminal 4 of the buffer device, i.e., of the semiconductor memory device is rapidly charged. Electric potential of the output terminal 4 is then pulled up to a HIGH level, that is, a level of the power source, as shown in FIG. 5 (d).
Next, when both address signals A0 and A1 change to a LOW level, the data "1" is read from address (0,0), and a HIGH signal S1 as shown in FIG. 5 (b) and corresponding to the data value "1" is inputted to the booster circuit 3 and the inverter 5. The electric potential of the output terminal 4 is then pulled up to the power source level as when both address signals A0 and A1 are HIGH.
However, when the address signals are skewed, i.e., when there is a slight difference in the transition timing of the address signal A0 and address signal A1 from a HIGH to a LOW level as shown in FIG. 5 (a), and there is a resulting transient period in which the address signal A0 is LOW and the address signal A1 is HIGH, the following problems result.
Specifically, when the address signals are skewed as described above, the data "0" is transiently read from address (0,1) as shown in FIG. 5 (b). As a result, a data signal S1 inputted to the booster circuit 3 has a LOW transient pulse P inserted between the signal S1 of a HIGH level corresponding to the data "1" read from address (1,1) and the signal S1 of a HIGH level corresponding to the data "1" read from address (0,0).
A symbol T in FIG. 5 (b) indicates a time lag between the address skew occurring in the transition to a LOW level and inputting of the LOW transient pulse P in the signal S1 to the buffer circuit.
When the transient LOW pulse P as described above is inputted, boosting of the signal S1 inputted after the LOW pulse P becomes insufficient, and the booster circuit 3 is unable to maintain a normal boost level in the output signal S2 from the output terminal 9 as shown in FIG. 5 (c)(i). Another possibility is that due to the booster circuit construction the signal S1 is not boosted when it should be boosted, and the level of the output signal S2 from the output terminal 9 remains LOW as shown in FIG. 5 (c)(ii). The problem is therefore that, as shown in FIG. 5 (d)(i) and (d)(ii), the level corresponding to the data "1" read from address (0,0) at the output terminal 4 is lower than a specified pull-up level.